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Edward Nevill
Day Sunday
Room AW1.125
Start time 13:15
End time 13:45
Duration 00:30
Event type Podium
Track Free Java
Language English
The ARM Optimised Interpreter and Thumb2 JIT

The ARM architecture in constrained devices such as smartphones and low end netbooks presents unique challenges for the VM writer. The ARM Optimised Interpreter delivers performance improvement of up to five times the C interpreter in the OpenJDK Zero port while maintaining smooth performance throughout. This talk looks at the techniques used and explores how they could be extended to other architectures.

The second part of the talk will look inside the Thumb2 JIT. The principle design goal of the Thumb2 JIT was to optimise time of first execution rather than peak performance. As such the design goals were to produce a JIT giving very fast compile time while generating reasonable and compact code.

The ARM architecture is typically used in constrained devices such as smartphones and low end netbooks. Typically a constrained device has

  • Single, not multiple core
  • Relatively fast core speed (800MHz)
  • Small primary cache (32K I+D)
  • Small secondary cache
  • Slow memory system (typically 300nS)
  • Small memory system (typically 512M)
This means that the system is almost completely constrained by the memory system. A single cache miss can cost up to 270 cycles. This presents particular challenges for the VM writer. A traditional JIT solution may not offer the best performance because of cache trashing. For larger applications the interpreter may actually offer better performance than a JIT. Over the past year I have been working on a project to improve the Java performance on these devices. I have implemented this by writing an optimised ARM Interpreter in hand crafted ARM assembler and coupling this with a Thumb2 JIT which interacts quickly and seamlessly with the interpreter.