RISC-V
Open Hardware for Your Open Source Software
- Track: Architectures
- Room: K.1.105 (La Fontaine)
- Day: Sunday
- Start: 13:00
- End: 13:50
RISC-V is a new open, royalty-free instruction set specification from the University of California, Berkeley that is finding its way into applications that range from IoT to supercomputing. With the advent of RISC-V, hardware implementers are now able to build fully open-source CPUs.
RISC-V distills over 30 years of RISC processor research at Berkeley and elsewhere into an extensible instruction set that can be fully customized. In this talk, we will discuss the goals of the RISC-V project and dig into the RISC-V instruction set. We will also give an overview of some popular open-source RISC-V hardware implementations as well as the RISC-V open-source software stack.
Speakers
| Arun Thomas |