A unique processor architecture meeting LLVM IR and the IoT
- Track: LLVM Toolchain devroom
- Room: K.3.401
- Day: Sunday
- Start: 16:20
- End: 17:00
A typical LLVM backend consists of complex passes lowering LLVM IR into valid and efficient machine code (MC). Complexity of the translation process originates from the inherent gap between LLVM IR and any mainstream instruction set architecture (ISA). Processors and their ISAs have been designed historically to be programmed by human assembly developers. Recent ISAs gained more complex features based on hardware considerations. To date, ISAs are designed with no respect for the IR of compilers. Hence, translation between IR and MC keeps being a complicated task. What about lifting the target machine to meet LLVM Assembly instead of lowering LLVM IR to meet an unrelated ISA? A lifted target machine can simplify backend development. One may wonder, however, what else can be gained from such an endeavor? The answers to these questions might be relevant for those who are interested in hardware architectures and likewise for those working with compiler and application development. This talk reveals how we realize a processor whose ISA is tailor-made to suit LLVM IR; what we expect from a rich ISA matching LLVM Assembly; and how we plan to utilize this technology to implement a multi-purpose architecture for IoT devices.
Imsys is a Swedish semiconductor SME with its proprietary processor architecture. Imsys processors provide a flexible, low-cost, and energy-efficient platform thanks to a microprogrammable microarchitecture implemented in the hardware core, which enables dynamic soft-reconfiguration as well. Imsys processor cores are small and energy-efficient by design as the architecture is mostly implemented in dense, low-power, read-only memory rather than in logic circuits. Operations are defined at a relatively high level of abstraction and coded in a way which results in an efficient utilization of the different parts of the core. Hence, silicon area and power consumption are minimized. The basic instruction set architecture (ISA) implemented in microcode is extensible with domain-specific instructions. Microcoded operations for signal processing and cryptographic features are already available for integration as special instructions or autonomous background processes in any ISA. That makes it possible to compile high-level software to an efficiently executed small footprint binary application. A new generation of processors is currently being developed with an ISA designed specifically for LLVM. ISAL, the Imsys ISA for LLVM, provides a set of instructions matching LLVM Assembly. Besides easing the development of a corresponding LLVM backend, the tailor-made rich ISA is expected to (1) provide outstanding code density and (2) propagate software complexity into highly efficient microcode implementation of ISAL instructions. Therefore, the LLVM toolchain can easily turn high-level software into high efficiency binary code with respect to memory footprint, execution time, and energy consumption. That can be done without worrying about target-specific details since the step between LLVM IR and ISAL machine code is minimal. The next generation Imsys processor featuring ISAL and a software ecosystem around it are planned to be released in 2018. The proposed lightning talk provides a brief insight into how it is possible with the help of microcoding to define ISAL so that it meets LLVM IR. Our driving incentives in selecting this way of action are also discussed, especially considering how an ISA designed for LLVM helps exploiting inherent characteristics of our processor technology in order to make the platform appealing in the IoT market.
Speakers
| Dávid Juhász |