Although some of the currently available SDRs come with means of adding FPGA based acceleration to boost performance, almost nobody is making use of them. One of several reasons for that is, that the learning curve is quite steep for a beginner.

This talk will briefly describe a way to add hardware acceleration to Zynq based SDRs, that has already been successfully used in Jonathon Pendlum's GSoC project.

I'll give an overview of where we are at the moment, what the development experience right now is like, what parts are still missing, and what I'm planning on adding.