Brussels / 3 & 4 February 2018


AMENDMENT Designing a Libre Embedded / Mobile RISCV64 SoC

Distillation of the best features and pin-multiplexing of commercial embedded / mobile processors

Please note that this replaces the talk by Rik Lempens on SiriDB - Time Series Database

In reaching out to the India Shakti RISC-V team the opportunity presented itself to put a proposal to them of a mobile / embedded RISC-V 64-bit SoC that would meet their requirements: low cost, libre, and suitable for four markets: smartphone, tablet, laptop / netbook and embedded industrial purposes. Six years ago the author attempted to create an SoC pinmux: it took over two months. Learning from that experience and instead writing a python program to represent the pinouts, adding new test scenarios instead took about an hour each, including altering the pinouts to best match the new scenario whilst still maintaining access to functions needed for all other scenarios as well. Assuming the market assessments were correct, the design - which only requires a 300-pin BGA package - can be said to have been proven to successfully meet all four target markets. Crucially with this approach, potential customers can be approached with the preliminary design, for their input and feedback before committing huge sums to design and tape-out actual silicon.

The output of the python program is a simple markdown page that can be used, without alteration, as the Reference Documentation should the SoC ever be created. In addition to the pinouts, the source of the design inspiration and guides utilised in the design has also been documented, so as to provide not just Reference Schematics and parts that are easily available in the Shenzhen / China markets, but also a logical justification for the actual choice of interfaces in each of the target usage scenarios. Ultimately, it helps explain why low-cost embedded and mobile-class processors are designed the way that they are.

Also included is links to numerous sources of BSD-licensed and compatible LGPL-licensed hard macros (VLSI / VHDL) such as the ORSOC Graphics Accelerator, so that, if utilised, apart from the DDR3 hard macros (which the Shakti team plan to implement under a libre license) the entire SoC's full hardware-design source code is completely available under Libre Licenses. With absolutely no proprietary firmware required whatsoever it has the potential to be one of the world's first ever mass-volume mobile-class quad-core 28nm 2.5ghz embedded SoCs that will be entirely libre right down to the bedrock.


Luke Kenneth Casson Leighton