Traditionally, the goal of digital hardware design has been to produce an ASIC. Ideally one which works perfectly after the first tapeout. Tailored towards this goal are our development and testing processes: strictly following a V-model with separated development and verification teams, long design iterations and code which, once it's known to work, is never touched again. For people coming from the software world, this development approach looks arcane. Where are all the sprints, the agile methods, the quick iterations?

With FPGAs being on the rise and available in more and more cloud data centers and possibly bundled with our next Intel processor, we finally get the chance to cheaply make mistakes in digital hardware designs: no more wasted tapeouts, just a new flashing of the FPGA is necessary to fix a bug.

Join me in this talk for a look at development processes and tools. Where can we build bridges between the software and hardware development world, and where do we have fundamentally different needs?