nmigen™ is a tool for creating hardware, whether for ASICs or for FPGAs. it is not itself an actual language (like Verilog or VHDL), and it is not like MyHDL which allows translation of a limited subset of python source code into verilog. Instead, nmigen allows you - in python - to create HDL constructs, and to mix those in with the full power of python OO techniques: objects, classes, even multiple inheritance, which is sorely lacking in the Hardware world.

this talk will go through the background and origins of nmigen, present a short worked-example, present some best-practices for people wishing to transfer over from another HDL, and cover some of the planned advancements.