The Composite CBOS is in many ways a traditional micro-kernel. Services and policies are implemented at user-level, the kernel focuses on fast IPC, and it uses a strong capability-based access control mechanism. It has historically focused on being a research laboratory for strange features including a thread-migration-based IPC, user-level scheduling of system-level threads, user-level definition of capability policies, a wait-free kernel that scales linearly with increasing cores, and temporal capabilities to coordinate between untrusting schedulers. It also scales down and supports paravirtualized RTOSes on microcontrollers (with on the order of 64KiB SRAM, between 16 and 200 Mhz, and MPUs). Composite represents a design that deviates from the L4 lineage in some interesting ways. In this talk, we'll discuss the design with a focus on how the system provides the challenging combination of predictability, performance, and scalable parallelism.