Brussels / 1 & 2 February 2020


Building Loosely-coupled RISC-V Accelerators

Using Chisel/FIRRTL to build accelerator templates and collateral for the ESP SoC platform

The burgeoning RISC-V hardware ecosystem includes a number of microprocessor implementations [1, 3] and SoC generation frameworks [1, 2, 7]. However, while accelerator “sockets” have been defined and used (e.g., Rocket Chip’s custom coprocessor/RoCC), accelerators require additional collateral to be generated like structured metadata descriptions, hardware wrappers, and device drivers. Requiring manual effort to generate this collateral proves both time consuming and error prone and is at odds with an agile approach to hardware design. However, the existence and use of hardware construction languages and hardware compilers provides a means to automate this process. Through the use of the Chisel hardware description language [4] and the FIRRTL hardware compiler [5], we provide a definition of an abstract accelerator template which users then implement to integrate an accelerator with the Embedded Scalable Platform (ESP) System-on-Chip platform [2, 8]. Through the use of this template, we are able to automatically generate XML metadata necessary to integrate accelerators with the ESP platform and work on generating all collateral is in progress. Our accelerator template is open source software provided under an Apache 2.0 license [6].

[1] CHIPS alliance Rocket-chip. GitHub Repository. Online:

[2] Columbia University Embedded scalable platform. git repository. Online:

[3] ETH Zurich Ariane. GitHub Repository. Online:

[4] Freechips Project Chisel3. GitHub Repository. Online:

[5] Freechips Project FIRRTL. GitHub Repository. Online:

[6] IBM ESP chisel acclerators. GitHub Repository. Online:

[7] Princeton University OpenPiton. GitHub Repository. Online:

[8] ESP: The open-source heterogeneous system-on-chip platform. Online:


Photo of Schuyler Eldridge Schuyler Eldridge