Brussels / 2 & 3 February 2019


How compact is compiled RISC-V code?

RISC-V is an increasingly popular architecture for embedded systems. For such systems, compiled code density is a critical factor, particularly for deeply embedded and low power systems, where memory may be very constrained. Architectures in this space are often designed to improve code density. Thus ARM has its Thumb-2 instructions and RISC-V has its compressed instructions.

If compiler tool chains are to generate compact code, we need to be able to measure how well we are doing. In this talk I shall present measurements of code density for 32-bit RISC-V, ARM and ARC architectures using the GCC and Clang/LLVM compiler tool chains using the BEEBS benchmark suite for deeply embedded systems ( I shall show how confounding factors (such as emulation library implementation and C run-time startup) can be eliminated from such measurements, to ensure the results are meaningful.

The purpose of this exercise is not to show that any one architecture is "best" but to provide insight which will drive compiler optimization for code density. I shall use the data to highlight areas where the RISC-V compiler tool chain can be improved, drawing on customer work carried out by Embecosm during 2018.


Photo of Jeremy Bennett Jeremy Bennett