FPGA Manager & devicetree overlays - Making FPGAs first class citizens in the upstream Linux Kernel

Static System on Chip (SoC) configurations commonly found in today's embedded systems can be easily described by devicetree files. These files provide the kernel with the necessary information about hardware devices, their connections, clocks, resets and other properties that could be either runtime probed, or would be provided by the BIOS on normal PC systems.

FPGAs have been present in embedded systems for a long time. Their reconfigurability allows for in-the-field upgrades to large parts of a system's functionality. For this kind of reconfigurability it is sufficient to reload the FPGA image once at boot, and to present the peripherals in the programmable logic parts to the Linux Kernel in the same way as any other hardware.

With FPGA based SoCs such as Altera's SocFPGA and Xilinx Zynq this model of reconfiguration poses its challenges, as runtime reconfiguration (and even partial reconfiguration) may cause parts of the fabric-based logic to temporarily (or permanently!) disappear. In that case presenting the FPGA based logic to the kernel might lead to issues as the corresponding device drivers don't get unloaded properly when the corresponding logic goes away.

Vendor trees (that contain modifications to the Linux Kernel, that have not been upstreamed) provide userland applications with a capability to reload the FPGA image. In this case a hybrid system with in kernel drivers and userland applications is quickly forced into using ugly hacks to make it all work together.

FPGA manager is a vendor-neutral framework currently under development (will be in 4.4), that allows reloading FPGA images in a safe, clean and intuitive manner, while nicely integrating with the Linux Kernel's driver model.

To model the dependencies of FPGA based IP in processor based SoC's the SimpleFPGA bus was developed. It allows to specify dependency topologies to reconfigure SoC busses at runtime, while dealing with issues such as runtime clock control, resets, as well as loading the correct (partial) bitstreams through FPGA Manager.

Originally developed to support the BeagleBone Black's capes that require runtime pinctrl, devicetree overlays can be used to change the Linux Kernel's representation of the devicetree at runtime. Recently merged into upstream devicetree overlays provide a very natural and clean way to describe modifications to the devicetree, while keeping the whole system in a coherent state.

This talk will give a brief intro to devicetree, the problems related to runtime reconfiguration and then describe the SimpleFPGA bus and FPGA Manager frameworks. Some simple examples using devicetree overlays will be given that will demonstrate why the three elements make for such a compelling combination.