Brussels / 31 January & 1 February 2015



An open RISC softcore for research and experimentation

BERI (the Bluespec Extensible RISC Implementation) is a softcore processor jointly developed by SRI International and The University of Cambridge. It implements a superset of the MIPS III ISA in Bluespec, a high-level HDL and supports a fully open source, permissively licensed, software stack comprising the FreeBSD operating system and the LLVM compiler suite. This talk will describe the design of the BERI processor and its use.

BERI was created to facilitate experimentation at the boundaries between CPU architecture, operating systems, and programming languages. It runs in Altera and Xilinx FPGAs, including the NetFPGA 10G board. At 100MHz, it is fast enough to use as a real computer (albeit a fairly slow one). This allows

There is a close tie between the history of UNIX-like systems and academic use. The original AT&T UNIX was distributed cheaply to universities and so formed the basis of both research projects and operating systems courses for a long time. MINIX, originally free for non-commercial use and now BSD licensed, was written primarily as a platform for teaching and research use and the ties between BSD and UCB speak for themselves. The open source community has benefitted enormously from people passing through university for almost three decades and studying UNIX and related systems.

Compiler development has seen a similar renaissance in recent years, primarily spurred by LLVM, which provides a set of libraries that are easy to use and to modify for building compilers for new languages and new platforms.

The one missing part of the puzzle, so far, has been the hardware. Although we have a plethora of commodity CPUs and even a number of open source designs, these have not typically well integrated into an open source stack.

This talk will discuss the BERI softcore, jointly developed by The University of Cambridge and SRI International and the associated open source software stack. BERI, the Bluespec Extensible RISC Implementation, is a 64-bit MIPS implementation in Bluespec, a high-level hardware description language. It implements the instruction set that debuted in the MIPS R4000 core in 1991, and therefore a set that is free of patents owing to its age. In spite of this, it is a relatively modern 64-bit architecture and is well supported by open source systems. The FreeBSD port to BERI required minimal changes, which were shipped as part of the FreeBSD 10.0 release, and runs unmodified userland 64-bit MIPS code. BERI can run in simulation at a speed acceptable for testing but not for general usage or in an FPGA at 100MHz. The BERI design supports multiple cores on a single FPGA and work is ongoing to support multicore across boards connected with a low-latency interconnect.

On top of this runs FreeBSD, a permissively licensed UNIX variant, and the LLVM compiler suite. This provides a solid platform for experimental use, as users can modify any aspect of the system, from the instruction set upwards. It is relatively simple, for example, to add a new set of instructions as a coprocessor to BERI, add code to the operating system so that the state is preserved across context switches, and add code generation support in LLVM.

BERI provides a generic coprocessor interface, which makes it very easy to extend the functionality. CHERI, Capability Hardware Enhanced RISC Instructions, is a BERI-based CPU that adds a coprocessor providing a capability-oriented memory model. This demonstrates the extensibility of the BERI stack: the CPU, operating system, and compiler have all been modified to provide support for new functionality.


Photo of Jonathan Woodruff Jonathan Woodruff