Although CORE-V is a completely standard RISC-V architecture, it supports a large number of custom ISA extensions, and it is the support of these extensions that creates most of the challenge. Many of these extensions come from the PULP research group at ETH Zürich, but some are pre-freeze versions of what will become standard RISC-V extensions.

The upstream projects generally provide mechanisms to support vendor specific variants, for example by use of the vendor field in the target triplet. Thus rather than the generic riscv32-unknown-elf-gcc compiler, we can have the riscv32-corev-elf-gcc compiler. However this requires modifications to the code to use this information to control when CORE-V specific functionality is to be enabled, and this talk will explore these. In one specific case (vendor specific relocations), we are waiting on standardization from the RISC-V psabi committee, but otherwise this is all using well proven existing technology.

The work has also served to expose gaps in the upstream projects. For example, while versioning of ISA extensions is standardized, the code base for the GNU assembler lacks the infrastructure to handle this. Similarly many ISA extensions require builtin (intrinsic) function support, but the upstream tools have only a handful of builtin functions, and the infrastructure for RISC-V builtins is very small.

The talk cannot cover detail of every tool and operating system being developed, so will concentrate particularly on the CORE-V GCC tool chain. However we will draw parallels with the work going on in CORE-V specific simulators and in CORE-V specific operating systems.