Brussels / 4 & 5 February 2023


Building FPGA Bitstreams with Open-Source Tools

Yosys and nextpnr made FPGA development very attractive for developers that prefer to use open-source tools over proprietary vendor tools. Affordable and well documented boards with ECP5 FPGAs lowered the entry threshold for hobbyists even further.

Michael will show how to use LiteX to use these tools to build soft-core RISC-V SoCs that are capable of running Linux and combine them with use-case specific cores to custom FPGA bitstreams.

LiteX provides a framework to build FPGA SoCs including a few examples of SoCs that are capable of running Linux. However, for fully leveraging the capabilities of FPGAs, one would not only reproduce existing designs, but also implement use-case specific cores and add them to the FPGA bitstream.

Michael will give an update on Steffen's and his experiences with using the open-source FPGA tools to build FPGA bitstreams. In recent years, they presented how to build the LiteX example SoCs, run Linux on them, and how to make the systems reproducible by using Yocto. This talk will focus on how to add custom cores that are written in Verilog and Migen to the SoC to implement use-case specific features.


Photo of Michael Tretter Michael Tretter