Brussels / 31 January & 1 February 2015


Adding VHDL support to Icarus Verilog

Have you ever wondered how simulators perform their tasks? Are you looking for a FOSS replacement for your proprietary simulator?

Icarus Verilog is a part of gEDA project. It is mostly known as a FOSS hardware description language simulator, although its capabilities reach beyond that. The name indicates it is a Verilog simulator, many features of SystemVerilog are already implemented and VHDL makes its way there.

If you want to hear about what else you can achieve with Icarus, how its internal gears are running, or possible ways to extend its functionality - feel invited.


Maciej SumiƄski