Using the ECP5 for Libre-SOC prototyping
- Track: Libre-SOC, FPGA and VLSI devroom
- Room: K.4.201
- Day: Saturday
- Start: 13:40
- End: 14:30
- Video only: k4201
- Chat: Join the conversation!
The Libre-SOC project has been prototyped using an Lattice ECP5 FPGA before its first tapeout. Since then many things have changed. One big change is the use of a different controller for DDR3 called gram. To get DDR3 working on the OrangeCrab many changes are needed.
This talk will provide an overview on my work on Libre-SOC in the past two years, an overview of DDR SDRAM interfaces and the PHYs commonly found on FPGAs and some ways to debug the OrangeCrab using a BeagleWire.
Speakers
Tobias Platen (they/them) |